FPGA Development and Evaluation Board
This tender has closed. It is published here as a public record.
- Buyer: Department of Higher Education
- Ministry: Ministry of Education
- Category: FPGA Development and Evaluation Board
- Location: Kalyanpur, Uttar Pradesh
- Delivery location: Kanpur
- Bid type: bid
- Published on: 09 Jul 2026
- Closed on: 27 Jul 2026, 06:00 pm IST
About this tender
FPGA Development and Evaluation Board (Q3) — total quantity 1. Delivery to 1 consignee location, 30 days delivery. MSE relaxations available; ±25% option clause on quantity.
Who can bid, EMD and how to apply
- Who can bid: any seller registered on the Government e-Marketplace for FPGA Development and Evaluation Board.
- EMD: as declared on GeM.
- Last date: closed on 27 Jul 2026, 06:00 pm IST.
- Where to apply: on GeM (bidplus.gem.gov.in). The bid number, documents and buyer details open with a free iBid.Win account.
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