FPGA Development and Evaluation Board

This tender has closed. It is published here as a public record.

• Buyer: Department of Space
• Category: FPGA Development and Evaluation Board
• Location: Thiruvanathapuram, Kerala
• Delivery location: Iist Kerala
• Bid type: bid
• Published on: 10 Aug 2026
• Closed on: 24 Aug 2026, 11:00 am IST

About this tender

FPGA Development and Evaluation Board (Q3) ( PAC Only ) — total quantity 2. ePBG 3% for 14 months. Delivery to 1 consignee location, 60 days delivery. ±25% option clause on quantity.

Who can bid, EMD and how to apply

• Who can bid: any seller registered on the Government e-Marketplace for FPGA Development and Evaluation Board.
• EMD: as declared on GeM.
• Last date: closed on 24 Aug 2026, 11:00 am IST.
• Where to apply: on GeM (bidplus.gem.gov.in). The bid number, documents and buyer details open with a free iBid.Win account.

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